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features ? 10-bit resolution adc 2.2 gsps sampling rate seamless ascending compatibility with ts83102g0b 10-bit 2 gsps adc 500 mvpp full-scale analog input range 100 ? differential or 50 ? single-ended analog input and clock input 100 ? differential outputs ecl/lvds output compatibility functions: ? adc gain adjust and sampling delay adjust ? data ready output with asynchronous reset ? out-of-range output bit power consumption: 4.2w power supplies: ? analog: -5v, 5v ? digital: -5v to -2.2v and 1.5v radiation tolerant package: cbga152 cavity down hermetic package evaluation board AT84AS008gl-eb companion device: ? dmux 10-bit 1:2/1:4 lvds 2.2 gsps at84cs001 performances ? 3.3 ghz full power input bandwidth (-3 db) ? gain flatness: 0.2 db (from dc up to 1.5 ghz) ? low input vswr: 1.2 maxi mum from dc to 2.5 ghz ? single tone performances (-1 dbfs): sfdr = -58 dbc; 8.0 enob; snr = 52 dbc at f s = 1.7 gsps, f in = 850 mhz sfdr = -54 dbc; 7.6 enob; snr = 50 dbc at f s = 2.2 gsps, f in = 1.1 ghz sfdr = -54 dbc, 7.4 enob; snr = 48 dbc at f s = 2.2 gsps, f in = 2 ghz ? dual tone performances (imd3), fs = 1.7 gps, (-7dbf s tone): (fin1 = 995 mhz, fin2 = 1005 mhz): imd3 = 64 dbf s (fin1 = 1545 mhz, fin2 = 1555 mhz): imd3 = 62 dbf s (fin1 = 1945 mhz, fin2 = 1955 mhz): imd3 = 59 dbf s ? low bit error rate (10 -11 ) at 2.2 gsps screening ? temperature range for packaged device: 0c < t c ; t j < 90c (commercial c grade) -20c < t c ; t j < 110c (industrial v grade) applications ? broadband direct rf down conversion ? wide band satellite receivers ? phased array antennas, radars and ecm ? high-speed instrumentation and high-speed acquisition systems ? high energy physics ? automatic test equipment 10-bit 2.2 gsps adc AT84AS008 5404a?bdc?11/06
2 5404a?bdc?11/06 AT84AS008 1. description the AT84AS008 10-bit 2.2 gsps adc allows accu rate digitization of high frequency signals thanks to the 3.3 ghz analog input bandwidth. the innovative design of the on-chip track and hold (t/h) and digitizing core lead to unprece- dented dynamic performance at a sampling rate of 2.2 ghz (over the full first nyquist zone). a 7.6 enob is achieved at 2.2 gsps in nyquist conditions, using gray encoded digital outputs for optimum snr performance. the AT84AS008 features an enhanced spectral purity and very low noise floor, independent on frequency and temperature. it is particularly well suited for performance enhancement (i.e. dithering). the AT84AS008 is fully compatible with ts83102g0b 10-bit 2 gsps adc, allowing zero-effort system improvement by plug-and-play replacement with the new part. figure 1-1. block diagram 2. functional description the AT84AS008 is a 10-bit 2.2 gsps adc. t he device includes a front-end track and hold stage (t/h), followed by an analog encoding stage (analog quantizer) which outputs analog residues resulting from analog quantization. successive banks of latches regenerate the analog residues into logical levels before entering an error correction circuitry and a resynchronization stage followed by 100 ? differential output buffers. the AT84AS008 works in fully differential mode from analog inputs up to digital outputs. a differential data ready output (dr/drb) is available to indicate when the outputs are valid and an asynchronous data ready reset ensures th at the first digitized data corresponds to the first acquisition. for sampling rates exceeding 2 gsps, the gray output encoding is recommended for optimum snr performance. logic block or orb d9 d9b d0 d0b dr drb pgeb b/gb analog quantizer track &hold clock generation vin vinb clk clkb drrb ga decb/ diode sda 50 50 50 50
3 5404a?bdc?11/06 AT84AS008 the control pin b/gb (a11 of cbga package) is pr ovided to select either a binary or gray data output format. the gain control pin ga (r9 of cbga package) is provided to adjust the adc gain transfer function. a samplin g delay adjust function (sda) is provided to fine tune the adc aperture delay, for applications requesting the in terleaving of multiple adcs for example. a pat- tern generator is integrated on chip for debug or acquisition set-up. this function is enabled through the pgeb pin (a9 of cbga package). an out of range bit (or,orb) indicates when the input overrides the adc full-scale range. a selectab le decimation by 32 function is also available for enhanced testability co verage (a10 of cbga package) al ong with a die junction temperature monitoring function. the AT84AS008 uses only vertical isolated npn transistors together with oxide isolated polysili- con resistors, which allows enhanced radiation tolerance (over 100 krad (si) expected total dose). the AT84AS008 provides full ascending compatibility with the ts83102g0b with enhanced performances. 3. specifications 3.1 absolute maximum ratings note: absolute maximum ratings are limiting values (referenced to gnd = 0v), to be applied individually, while other parameters are within specified operating conditions. long exposure to maximum rating may affect device reliability. all integrated circuits have to be handled with appropriate care to avoid damages due to esd. damage caused by inappropriate handling or storage could range from performance degradation to complete failure. table 3-1. absolute maximum ratings parameter symbol comments value unit positive supply voltage v cc gnd to 6.0 v digital negative supply voltage d vee gnd to -5.7 v digital positive supply voltage v plusd gnd -1.1 to 2.5 v negative supply voltage v ee gnd to -5.5 v max difference between digital voltages v plusd - d vee 7v maximum difference between negative supply voltages d vee to v ee 0.3 v analog input voltages v in or v inb -1.5 to 1.5 v maximum difference between v in and v inb v in - v inb -1.5 to 1.5 v clock input common mode voltage (v clk + v clkb )/2 -1.5 to 0.6 v maximum difference between v clk and v clkb v clk - v clkb -1 to 1 vpp static input voltage v d ga, sda -1 to 0.8 v digital input voltage v d sdaen, drrb, b/gb, pgeb, decb -5 to 0.8 v digital output voltage v o v plusd min operating -2.2 to v plusd max operating + 0.8 v junction temperature t j 130 c
4 5404a?bdc?11/06 AT84AS008 3.2 recommended c onditions of use notes: 1. adc performances are independent on v plusd common mode voltage and performanc es are guaranteed in the limits of the specified v plusd range (from -0.9v to 1.7v). 2. to save power d vee can be raised up to -2.2v as long as difference between v plusd and d vee remains greater than 3.5v. table 3-2. recommended conditions of use parameter symbol comments min typ max unit positive supply voltage v cc 4.75 5 5.25 v positive digital supply voltage (1) v plusd differential ecl output co mpatibility -0.9 -0.8 -0.7 v v plusd lvds output compatibility 1.375 1.45 1.525 v v plusd grounded v plusd maximum operating v plusd 1.7 v negative supply voltages v ee -5.25 -5.0 -4.75 v negative supply voltages d vee -5.25 -5.0 -4.75 v negative supply voltages d vee recommended to save power when vplus is above 1.4v (2) -2.3 -2.2 -2.1 v differential analog input voltage (full-scale) v in - v inb 100 ? differential or 50 ? single-ended (vinb grounded) 500 750 mv mvpp clock input power level (ground common mode) p clk , p clkb 50 ? single-ended clock input impedance or 100 ? differential input (recommended) -4 0 4 dbm operating temperature range commercial c grade industrial v grade 0c < t c ; t j < 90c -20c < t c ; t j < 110c c storage temperature tstg -65 to 150 c
5 5404a?bdc?11/06 AT84AS008 3.3 electrical characteristics v cc = 5v; v ee = d vee = -5v (unless otherwise specified): adc performances are independent of v plusd and d vee common mode voltage and performances are guaranteed in the limit of the specified v plusd range (from -0.9v to 1.7v) and d vee range (from v ee to -2.1v, as long as v plusd -v ee > 3.5v) v in - v inb = 500 mvpp (full-scale single-ended or differential input). clock inputs differential driven; analog-input single-ended driven table 3-3. electrical operating characteristics at ambient temperatures and hot temperatures parameter test level symbol min typ max unit resolution 10 bits power requirements power supply voltage - analog - digital (ecl) - digital (lvds) 1 1 4 v cc v plusd v plusd 4.75 5 -0.8 1.45 5.25 v v v power supply current - analog - digital ecl lvds (d vee = -2.2) lvds (d vee = -5) 1 1 1 1 i vcc i vplusd i vplusd i vplusd 80 180 160 250 100 220 200 300 ma ma ma ma negative supply voltage - analog - digital 1 1 v ee d vee -5.25 -5.25 -5 -5 -4.75 -4.75 v v negative supply current - analog - digital ecl lvds (d vee = -2.2) lvds (d vee = -5) 1 1 1 1 i vee i dvee i dvee i dvee 620 180 160 250 660 220 200 300 ma ma ma ma power dissipation ecl lvds (d vee = -2.2) lvds (d vee = -5) 1 1 1 p d 4.2 4.0 5.0 4.9 4.8 5.9 w w w analog inputs full-scale input voltage range (differential mode) (0v common mode voltage) 4 4 v in, v inb -125 -125 125 125 mv mv full-scale input voltage range (single-ended input option other input grounded) 4 4 v in, v inb -250 0 250 mv mv analog input power level (50 ? single-ended) 4 p in -2 dbm analog input capacitance (die) 4 c in 0.3 pf input leakage current 4 i in 10 a input resistance - single-ended - differential 4 4 r in r in 49 98 50 100 51 102 ? ?
6 5404a?bdc?11/06 AT84AS008 clock inputs logic common mode compatibility for clock inputs differential ecl to lvds clock inputs common voltage range (v clk or v clkb ) (dc coupled clock input) ac coupled for lvds com patibility (common mode 1.2v) 4v cm -1.2 0 0.3 v clock input power level (low-phase noise sinewave input) 50 ? single-ended or 100 ? differential 4p clk -4 0 4 dbm clock input swing (single ended; with clkb = 50 ? to gnd) 4v clk 200 320 500 mv clock input swing (differential voltage) - on each clock input 4 v clk v clkb 141 226 354 mv clock input capacitance (die) 4 c clk 0.3 pf clock input resistance - single-ended - differential ended 4 4 r clk r clk 45 90 50 100 55 110 ? ? digital inputs (sdaen, pgeb, decb/diode, b/gb) - logic low - logic high 4 v il v ih -5 -2 -3 0 v v digital inputs (drrb only) logic compatibility negative ecl - logic low - logic high 4 v il v ih -1.810 -1.165 -1.625 -0.880 v v digital outputs (1) logic compatibility (depending on v plusd value) differential ecl (v plusd = -0.8v typical) output levels 50 ? transmission lines, 100 ? (2 50 ? ) differentially terminated - logic low - logic high - swing (each single-ended output) - common mode 1 1 1 1 v ol v oh v oh - v ol -0.99 200 -1 -1.24 -0.96 260 -1.1 -1.15 300 -1.15 v v mv v logic compatibility (depending on v plusd value) lvds (v plusd = 1.45v typical) d vee = -2.2v output levels 50 ? transmission lines, 100 ? (2 50 ? ) differentially terminated - logic low - logic high - swing (each single-ended output) - common mode (4) ...... max v plusd = 1.525v ...... typ v plusd = 1.45v ...... min v plusd = 1.375v 4 4 4 4 4 4 v ol v oh v oh - v ol 1250 200 1010 1050 1280 240 1160 1100 280 1310 mv mv mv mv mv mv table 3-3. electrical operating characteristics at ambient temperatures and hot temperatures (continued) parameter test level symbol min typ max unit
7 5404a?bdc?11/06 AT84AS008 notes: 1. differential output buffers impedance = 100 ? differential (50 ? single-ended). 2. histogram testing at fs = 390 msps fin = 100 mhz. 3. the adc gain can be fine tuned to 1 thanks to the gain adjust function. 4. the output common mode only depends on v plusd value and can thus be adjusted accordingly. logic compatibility (depending on v plusd value) lvds (v plusd = 1.45v typical) d vee = - 5v output levels 50 ? transmission lines, 100 ? (2 50 ? ) differentially terminated - logic low - logic high - swing (each single-ended output) - common mode (4) ...... max v plusd = 1.525v ...... typ v plusd = 1.45v ...... min v plusd = 1.375v 1 1 1 4 1 4 v ol v oh v oh - v ol 1160 325 880 840 1220 375 1030 900 450 1180 mv mv mv mv mv mv dc accuracy dnlrms 1 dnlrms 0.2 0.3 lsb differential non-linearity (2) 1dnl+ 0.8 1.5lsb integral non-linearity (2) 1inl--4-2.5 lsb integral non-linearity (2) 1inl+ 2.5 4 lsb gain central value (3) 1 0.9 1 1.1 gain error drift 4 23 35 ppm/c input offset voltage 1 -10 10 mv table 3-3. electrical operating characteristics at ambient temperatures and hot temperatures (continued) parameter test level symbol min typ max unit table 3-4. ac electrical characteristics at ambient temperatures and hot temperatures (t j max) parameter test level symbol min typ max unit ac analog inputs full power input bandwidth (1) 4 fpbw 3.3 ghz small signal input band width (10% full-scale) 4 ssbw 3.5 ghz gain flatness (2) 4bf 0.20.3db input voltage standing wave ratio (3) 4 vswr 1.1:1 1.2:1 ac performance: nominal condition at ambient and hot temperature tj max -1 dbf s single ended input mode (unles s otherwise specif ied), 50% clock duty cycle, 0dbm di fferential clock (clk, clkb), binary output data format. signal-to-noise and distortion ratio fs = 1.4 gsps ...... fin = 700 mhz fs = 1.7 gsps ...... fin = 1.7 ghz fs = 2.2 gsps ...... fin = 1.1 ghz fs = 2.2 gsps ...... fin = 2.0 ghz 1 4 4 4 sinad 46 44 43 43 49 47 47 46 dbc
8 5404a?bdc?11/06 AT84AS008 notes: 1. see ?definition of terms? on page 31. 2. from dc to 1.5ghz 3. specified from dc up to 2.5 ghz input signal. input vswr is measured on a soldered device. it assumes an external 50 ? 2 ? controlled impedance line, and a 50 ? driving source impedance (s 11 < -30 db). effective number of bits fs = 1.4 gsps ...... fin = 700 mhz fs = 1.7 gsps ...... fin = 1.7 ghz fs = 2.2 gsps ...... fin = 1.1 ghz fs = 2.2 gsps ...... fin = 2.0 ghz 1 4 4 4 enob 7.4 7.2 7.1 7.0 8.0 7.7 7.6 7.4 bit signal to noise ratio fs = 1.4 gsps ...... fin = 700 mhz fs = 1.7 gsps ...... fin = 1.7 ghz fs = 2.2 gsps ...... fin = 1.1 ghz fs = 2.2 gsps ...... fin = 2.0 ghz 1 4 4 4 snr 49 46 46 45 52 49 50 48 dbc total harmonic distortion (25 harmonics) fs = 1.4 gsps ...... fin = 700 mhz fs = 1.7 gsps ...... fin = 1.7 ghz fs = 2.2 gsps ...... fin = 1.1 ghz fs = 2.2 gsps ...... fin = 2.0 ghz 1 4 4 4 |thd| 46 47 45 45 52 52 49 50 dbc spurious free dynamic range fs = 1.4 gsps ...... fin = 700 mhz fs = 1.7 gsps ...... fin = 1.7 ghz fs = 2.2 gsps ...... fin = 1.1 ghz fs = 2.2 gsps ...... fin = 2.0 ghz 1 4 4 4 |sfdr| 50 52 48 48 58 58 54 54 dbc two-tone third order inter-modulation distortion fs = 1.7 gsps (-7 dbf s each tone) - fin1 = 995 mhz; fin2 = 1005 mhz - fin1 = 1545 mhz; fin2 = 1555 mhz - fin1 = 1945 mhz; fin2 = 1955 mhz 4 4 4 |imd3| 64 62 59 dbfs table 3-4. ac electrical characteristics at ambient temperatures and hot temperatures (t j max) (continued) parameter test level symbol min typ max unit table 3-5. transient and switching performances parameter test level symbol min typ max unit transient performance bit error rate (1) 4 ber 10 -11 error/ sample adc settling time (vin-vinb = 400 mvpp) 4 ts 400 ps overvoltage recovery time 4ort 500ps adc step response rise/fall time (10/90%) 4 80 100 ps overshoot 54% ringback 52%
9 5404a?bdc?11/06 AT84AS008 notes: 1. output error amplitude < 6 lsb. fs = 2.2gsps tj = 110 c 2. see ?definition of terms? on page 31. 3. 50 ? // c load = 2 pf termination (for each single-ended output). term ination load parasitic capacitance derating value: 50 ps/pf (ecl). see ?timing information? on page 33. 4. tod and tdr propagation times are defined at package input/outputs. they are given for reference only 5. values for td1 and td2 are given for a 2.2 gsps external clock frequency (50% duty cycle). for different sampling rates, apply the following formula: td1 = t/2 +(|tod-tdr|) and td2 = t/2 +(|tod-tdr|), where t = clock period. this places the rising edge (true-false) of the differential data ready signal in t he middle of the output data valid window. this gives maximum setup and hold times for external data acquisition. 3.4 explanation of test levels only minimum and maximum values are guaranteed (typical values are issuing from characterization results). notes: 1. unless otherwise specified. 2. refer to ?ordering information? on page 45 . switching performance and characteristics maximum clock frequency (2) fs max 2.2 gsps minimum clock frequency (2) 4 fs min 200 msps minimum clock pulse width (high) 4 tc1 0.22 2.5 ns minimum clock pulse width (low) 4 tc2 0.22 2.5 ns aperture delay (2) ) 4 ta 160 ps aperture uncertainty (2) 4 jitter 150 200 fs rms output rise/fall time for data (20%-80%) (3) 4tr/tf 80110ps output rise/fall time for data ready (20%- 80%) (3) 4tr/tf 80110ps data output delay (4) 4tod 360 ps data ready output delay (4) 4tdr 360 ps 4 |tod-tdr| -50 0 +50 ps output data to data ready propagation delay (5) 4 td1 200 250 250 ps data ready to output data propagation delay (5) 4 td2 150 200 250 ps output data pipeline delay 4tpd 4.0 clock cycles data ready reset delay 4 trdr 300 ps table 3-5. transient and switching performances (continued) parameter test level symbol min typ max unit table 3-6. explanation of test levels 1 100% production tested at +25c (1) (for c temperature range (2) ) 2 100% production tested at +25c (1) , and sample tested at specified temperatures (for v temperature ranges (2) ) 3 sample tested only at specified temperatures 4 parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature) 5 parameter is a typical value only guaranteed by design only
10 5404a?bdc?11/06 AT84AS008 3.5 functions description table 3-7. functions description name function v cc positive power supply: 5v v plusd positive power supply for buffers:-0.8v => ecl; 1.45v => lvds v ee negative power supply: -5v d vee negative power supply for buffers:-5v or -2.2v (if lvds output logic) vin,vinb differential analog input clk,clkb differential clock input [d0:d9][d0b:d9b] differential output data. or, orb differential out of range dr,drb differential data ready drrb active low data ready reset pgeb active low pattern generator enable sda sampling delay adjust input sdaen active low sampling delay adjust enable ga gain adjust input decb/diode active low decimator enable and diode for die junction temperature monitoring 10 AT84AS008 gnd vin vinb sda drrb clk clkb d0..d9 d0b..d9b or, orb dr, drb vdiode sdaen decb/diode b/gb pgeb ga v ee = -5v v eed = -5v v cc = 5v v plusd = 1.45v
11 5404a?bdc?11/06 AT84AS008 3.6 timing diagram figure 3-1. timing diagram detailed timing diagram is provided in section 3.6 on page 11 . pipeline delay = 4 clock cycles tod td1 td2 tdr gray to binary decoding logic encoding n n+1 n+2 n n+1 n+2 n n+1 n+2 n n+1 n+2 n n+1 n+2 n n+1 n+2 n n+1 n+2 latch 1 latch 2 latch 3 latch 4 latch 5 latch 6 latch 8 latch 9 data read y out p uts internal clock external clock analog input output latches regeneration latches ta n n+1 gray to binary decoding n n+1 n+2 latch 7 n+2 n+1 n 3.7 coding table 3-8. adc coding table differential analog input voltage level digital output binary (b/gb = gnd or floating) msb???....lsb out-of-range gray (b/gb = v ee ) msb???....lsb out-of-range > + 250.25 mv >top end of full-scale + ? lsb 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 + 250.25 mv + 249.75 mv top end of full-scale + ? lsb top end of full-scale - ? lsb 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 + 125.25 mv + 124.75 mv 3/4 full-scale + ? lsb 3/4 full-scale - ? lsb 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 + 0.25 mv -0.25 mv midscale + ? lsb midscale - ? lsb 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -124.75 mv -124.25 mv 1/4 full-scale + ? lsb 1/4 full-scale - ? lsb 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 -249.75 mv -250.25 mv bottom end of full-scale + ? lsb bottom end of full-scale - ? lsb 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 < -250.25 mv < bottom end of full-scale - ? lsb 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1
12 5404a?bdc?11/06 AT84AS008 4. characterization results 4.1 nominal conditions unless otherwise specified: v cc = 5v, v ee = -5v, v plusd = 1.45v tj = 80c 50% clock duty cycle, binary output data format -1 dbfs analog input 4.2 full power input bandwidth analog input level = -1 dbfs gain flatness at -0.5 db from dc to 1.5 ghz figure 4-1. full power input bandwidth at -3 db 4.3 vswr versus input frequency figure 4-2. vswr curve for the analog input (vin) and clock (clk) -6,0 -5,5 -5,0 -4,5 -4,0 -3,5 -3,0 -2,5 -2,0 -1,5 -1,0 -0,5 0,0 100 300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 3100 3300 3500 3700 3900 fin (mhz) dbfs -3 db bandwidth -0.5 db gain flatness 1,0 1,1 1,2 1,3 1,4 1,5 1,6 1,7 0 500 1000 1500 2000 2500 3000 350 frequency (mhz) vswr vin clk
13 5404a?bdc?11/06 AT84AS008 4.4 step response tr measured = 115 ps = sqrt(tr pulsegenerator 2 + tr adc 2 ) tr pulsegenerator (estimated) = 41 ps actual tr adc = 107 ps figure 4-3. step response rise time (fs = 2.2 gsps, fin = 1.1 ghz) 4.5 dynamic performanc e versus sampling frequency figure 4-4. dynamic parameters versus sampling frequency in nyquist conditions (fin = fs/2) -200 -100 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 100 200 300 400 500 600 700 800 900 1000 time (ps) lsb 0% 100% 10% 90% 0 1 2 3 4 5 6 7 8 9 10 1400 1600 1800 2000 2200 fs (msps) enob (bit) -90 -80 -70 -60 -50 -40 -30 -20 1400 1600 1800 2000 2200 fs (msps) sfdr (dbc) dependent and independent sfdr sfdr without the first 4 harmonics -90 -80 -70 -60 -50 -40 -30 -20 1400 1600 1800 2000 2200 fs (msps) thd (db) 20 30 40 50 60 70 80 90 1400 1600 1800 2000 2200 fs (msps) snr (db)
14 5404a?bdc?11/06 AT84AS008 4.6 dynamic performanc e versus input frequency figure 4-5. dynamic parameters versus input freq uency at fs = 1.7 gsps and 2.2 gsps figure 4-6. sfdr (minus the first 4 harmonics) vers us input frequency at fs = 1.7 gsps and 2.2 gsps 6 7 8 9 10 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 fin (mhz) enob (bit) -90 -80 -70 -60 -50 -40 -30 -20 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 fin (mhz) sfdr (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 fin (mhz) thd (dbfs) 40 42 44 46 48 50 52 54 56 58 60 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 fin (mhz) snr (dbfs) fs = 1.7 gsps, -1 dbfs analog input fs = 1.7 gsps, -6 dbfs analog input fs = 2.2 gsps, -1 dbfs analog input fs = 2.2 gsps, -6 dbfs analog input -90 -80 -70 -60 -50 -40 -30 -20 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 fin (mhz) sfdr (dbfs) fs = 1.7 gsps, -1 dbfs analog input fs = 2.2 gsps, -1 dbfs analog input
15 5404a?bdc?11/06 AT84AS008 4.7 signal spectrum figure 4-7. fs = 1.7 gsps, fin = 848 mhz, and 1698 mhz, -1 dbfs analog input, 32 kpoint fft figure 4-8. fs = 1.9 gsps, fin = 948 mhz and 1899 mhz, -1 dbfs analog input, 32 kpoint fft figure 4-9. fs = 2.2 gsps, fin = 1098 mhz and 1998 mhz, -1 dbfs analog input, 32 kpoint fft -160 -140 -120 -100 -80 -60 -40 -20 0 20 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 mhz dbc h1 fundamental (fin = 848 mhz) fs = 1.7 gsps sfdr (h5) -160 -140 -120 -100 -80 -60 -40 -20 0 20 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 mhz dbc h1 fundamental (1700 mhz - 1698 mhz = 2 mhz) sfdr (h2) -160 -140 -120 -100 -80 -60 -40 -20 0 20 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 mhz dbc h1 fundamental (1900 mhz - 1899 mhz = 1 mhz) sfdr (h2) -140 -120 -100 -80 -60 -40 -20 0 20 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 mhz dbc h1 fundamental (fin = 948 mhz) fs = 1.9 gsps sfdr (h2) -160 -140 -120 -100 -80 -60 -40 -20 0 20 0 100 200 300 400 500 600 700 800 900 1000 1100 mhz dbc h1 fundamental (fin = 1098 mhz) fs = 2.2 gsps sfdr (h3) -160 -140 -120 -100 -80 -60 -40 -20 0 20 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 mhz dbc h1 fundamental (2200 mhz - 1998 mhz = 202 mhz) sfdr (h3)
16 5404a?bdc?11/06 AT84AS008 4.8 dynamic performance sensitivity versus temperature and power supply figure 4-10. dynamic parameters versus junction temperature at fs = 1.7 gsps, fin = 848 mhz, -1 dbfs analog input figure 4-11. dynamic parameters at min., typ. and max. power supplies, -1 dbfs analog input note: min. power supplies: v cc = 4.75,v v ee = -4.75v, v plusd = 1.375v typ. power supplies: v cc = 5v, v ee = -5v, v plusd = 1.45v max. power supplies: v cc = 5.25v, v ee = -5.25v, v plusd = 1.525v 2 3 4 5 6 7 8 9 10 10 20 30 40 50 60 70 80 90 100 110 tj (?c) enob (bit) -90 -80 -70 -60 -50 -40 -30 -20 10 20 30 40 50 60 70 80 90 100 110 tj (?c) sfdr (dbc) -90 -80 -70 -60 -50 -40 -30 -20 10 20 30 40 50 60 70 80 90 100 110 tj (?c) thd (db) 20 30 40 50 60 70 80 90 10 20 30 40 50 60 70 80 90 100 110 tj (?c) snr (db) 2 3 4 5 6 7 8 9 10 min. power supplies typ. power supplies max. power supplies enob (bit) -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 -50 -48 -46 -44 -42 -40 min. power supplies typ. power supplies max. power supplies sfdr (dbc) -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 -50 -48 -46 -44 -42 -40 min. power supplies typ. power supplies max. power supplies thd (db) 40 42 44 46 48 50 52 54 56 58 60 min. power supplies typ. power supplies max. power supplies snr (db) 1.7 gsps 848 mhz 2.2 gsps 1098 mhz
17 5404a?bdc?11/06 AT84AS008 4.9 sfdr performance with and without added dither the dither profile has to be defined according to the adc's inl pattern as well as the trade-off to be reached between the increase in sfdr and the loss in snr, as described in figure 4-12 please refer to the application note on dither for more information. figure 4-12. sfdr and snr (dbc and dbfs) with and without added dither (-17 dbm dc to 5 mhz out of band dither) versus analog input power at fs = 1.7 gsps, fin = 710 mhz 4.10 dual tone performance figure 4-13. dual tone signal spectrum at fs = 1. 7 gsps, fin1 = 995 mhz, fin2 = 1005 mhz (-7 dbfs), imd3 = 68 dbfs. -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 fin level (db_fs) sfdr (dbc or dbfs) sfdr dbc without dither sfdr dbc with dither -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 fin level (db_fs) snr (db or dbfs) snr db without dither snr db with dither -140 -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 fs (mhz) dbfs f2 = fs - fin2 = 695 mhz - 7 dbfs f1 = fs - fin1 = 705 mhz - 7 dbfs imd3 2f1 - f2 = 715 mhz - 68 dbfs 2f2 - f1 = 715 mhz - 72 dbfs f1 - f2 = 10 mhz - 73 dbfs f1 + 2f2 = 395 mhz - 71 dbfs 2f1 + f2 = 405 mhz - 69 dbfs
18 5404a?bdc?11/06 AT84AS008 figure 4-14. dual tone signal spectrum at fs = 1.7 gsps, fin1=1545 mhz, fin2 = 1555 mhz (-7 dbfs), imd3 = 64 dbfs. figure 4-15. dual tone signal spectrum at fs = 1.7 gsps, fin1 = 1945 mhz, fin2 = 1955 mhz (-7 dbfs), imd3 = 59 dbfs figure 4-16. dual tone signal spectrum at fs = 2.2 gsps, fin1 = 1015 mhz, fin2 = 1025 mhz (-7 dbfs), imd3 = 62 dbfs. -140 -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 fs (mhz) dbfs f2 = fs - fin2 = 145 mhz - 7 dbfs f1 = fs - fin1 = 155 mhz - 7 dbfs imd3 2f1 - f2 = 165 mhz - 65 dbfs 2f2 - f1 = 135 mhz - 64 dbfs f1 - f2 = 10 mhz - 73 dbfs f1 + 2f2 = 445 mhz - 77 dbfs 2f1 + f2 = 455 mhz - 75 dbfs f1 + f2 = 300 mhz - 73 dbfs -140 -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 fs (mhz) dbfs f2 = fs - fin2 = 255 mhz - 7 dbfs f1 = fs - fin1 = 245 mhz - 7 dbfs imd3 2f2 - f1 = 265 mhz - 59 dbfs 2f1 - f2 = 235 mhz - 60 dbfs f2 - f1 = 10 mhz - 64 dbfs f1 + 2f2 = 755 mhz - 69 dbfs 2f1 + f2 = 745 mhz - 69 dbfs f1 + f2 = 500 mhz - 71 dbfs -140 -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 fs (mhz) dbfs f2 = fs - fin2 = 1015 mhz - 7 dbfs imd3 2f1 - f2 = 1035 mhz - 62 dbfs 2f2 - f1 = 1005 mhz - 63 dbfs f1 - f2 = 10 mhz - 62 dbfs f1 + 2f2 = 855 mhz - 62 dbfs 2f1 + f2 = 865 mhz - 63 dbfs f1 + f2 = 160 mhz - 63 dbfs f1 = fs - fin1 = 1025 mh z - 7 dbfs
19 5404a?bdc?11/06 AT84AS008 figure 4-17. dual tone signal spectrum at fs = 2. 2 gsps, fin1= 1545 mhz, fin2 = 1555 mhz (-7 dbfs), imd3 = 64 dbfs. figure 4-18. dual tone signal spectrum at fs= 2. 2 gsps, fin1=1945 mhz, fin2 = 1955 mhz (-7 dbfs), imd3 = 63 dbfs. 4.11 npr performance figure 4-19. digitizing of 575 mhz broadband pattern @ 1.4 gsps, 25 mhz notch centered around 290 mhz, -12 dbfs loading factor. -140 -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 10001050 1100 fs (mhz) dbfs f2 = fs - fin2 = 645 mhz - 7 dbfs imd3 2f1 - f2 = 665 mhz - 64 dbfs 2f2 - f1 = 635 mhz - 65 dbfs f1 - f2 = 10 mhz - 65 dbfs f1 + 2f2 = 245 mhz - 67 dbfs 2f1 + f2 = 255 mhz - 72 dbfs f1 + f2 = 900 mhz - 59 dbfs f1 = fs - fin1 = 655 mhz - 7 dbfs -140 -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 100010501100 fs (mhz) dbfs f2 = fs - fin2 = 245 mhz - 7 dbfs imd 3 2f1 - f2 = 265 mhz - 63 dbfs 2f2 - f1 = 235 mhz - 64 dbfs f1 - f2 = 10 mhz - 78 dbfs f1 + 2f2 = 745 mhz - 66 dbfs 2f1 + f2 = 755 mhz - 64 dbfs f1 + f2 = 500 mhz - 63 dbfs f1 = fs - fin1 = 255 mhz - 7 dbfs -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 f(mhz) db 25 mhz npr = 4 0,22 db filter cut off 25 mhz fs
20 5404a?bdc?11/06 AT84AS008 5. pin description table 5-1. pin description (cbga 152) symbol pin number function power supplies v cc k1, k2, j3, k3, b6, c6, a7, b7, c7, p8, q8, r8 5v analog supply (connected to same power supply plane) gnd b1, c1, d1, g1, m1, q1, b2, c2, d2, e2, f2, g2, n2, p2, q2, a3, b3, d3, e3, f3, g3, n3, p4, q4, r4, a5, p5, q5, p6, q6, p7, q7, r7, b9, b10, b11, r11, p12, a14, b14, c14, g14, k14, p14, q14, r14, b15, q15, b16, q16 analog ground v ee h1, j1, l1, h2, j2, l2, m2, c3, h3, l3, m3, p3, q3, r3, a4, b4, c4, b5, c5, a8, b8, c8, c9, p9, q9, c10, q10, r10 -5v analog supply (connected to same power supply plane) v plusd p10, c11, p11, q11, a12, b12, c12, q12, r12, d14, e14, f14, l14, m14, n14 digital positive supply d vee a13, b13, c13, p13, q13, r13, h14, j14 -5v or -2.2v digital power supply analog inputs vin r5 in-phase (+) analog input signal of the differential sample and hold preamplifier vinb r6 inverted phase (-) analog input signal of the differential sample and hold preamplifier clock inputs clk e1 in-phase (+) clock input clkb f1 inverted phase (-) clock input digital outputs d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 d16, e16, f16, g16, j16, k16, l16, m16, n16, p16 in-phase (+) digital outputs d0 is the lsb, d7 is the msb d0b, d1b, d2b, d3b, d4b, d5b, d6b, d7b, d8b, d9b d15, e15, f15, g15, j15, k15, l15, m15, n15, p15 inverted phase (-) digital outputs or c16 in-phase (+) out-of-range output orb c15 inverted phase (-) out-of-range output dr h16 in-phase (+) data ready signal output drb h15 inverted phase (-) data ready signal output additional functions b/gb a11 binary or gray select output format control - binary output format if b/gb is floating or connected to gnd - gray output format if b/gb is connected to v ee
21 5404a?bdc?11/06 AT84AS008 decb / diode a10 decimation function enable or die junction temperature measurement: - decimation active when low (die junction temperature monitoring is then not possible) - normal mode when high or left floating die junction temperature monitoring when current is applied pgeb a9 active low pattern generator enable - digitized input delivered at outputs according to b/gb if pgeb is floating or connected to gnd - checker board pattern delivered at outputs if pgeb is connected to v ee drrb n1 asynchronous data ready reset function (active at ecl low level) ga r9 gain adjust sda a6 sampling delay adjust sdaen p1 sampling delay adjust enable inactive if floating or connected to gnd active if connected to v ee table 5-1. pin description (cbga 152) (continued) symbol pin number function
22 5404a?bdc?11/06 AT84AS008 figure 5-1. cbga152 pinout notes: 1. if required, 4 nc balls can be electric ally connected to gnd if simplifying pcb routing. 2. the pinout is given with a bottom view. the way the columns and rows were defined is dif- ferent from the jedec standard. 5.1 package description 5.1.1 hermetic cbga 152 outline dimensions ceramic body size: 21 21 mm ball pitch: 1.27 mm cofired: al2o3 optional: discrete capacitor mounting lands on top side of package for extra decoupling. AT84AS008 cbga 152 bottom view decb/ diode pgeb orb or abcdefghj kl mnpqr abcdefghj kl mnpqr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
23 5404a?bdc?11/06 AT84AS008 figure 5-2. mechanical description bottom view 5.1.2 mechanical up view figure 5-3. isometric view metalic cap 9.27 x 9.27 mm chamfer 0.4 (x 4) 1 pin a1 index (no ball) a 21.00 mm 0.20 152 x o d = 0.80 0.10 mm 0.20 0.15 t t a b (position of array of columns/ref a and b) (position of balls within array) 1.27 mm pitch 21.00 mm 0.20 - b - - a -
24 5404a?bdc?11/06 AT84AS008 figure 5-4. package top view figure 5-5. package top view with optional discrete capacitors note: for additional decoupling of the power supplies, extra land capacitors have been foreseen as shown in this scheme. they are not needed if evaluation board decoupling recommendations are followed and if standard power supply are used (no switched power supply). performance results of the device have proven to be equiva lent with / without these capacitors. 4.335 mm marking area 1 21.00 mm sq 4.335 mm marking area 2 6.815 mm cuw 7.2 mm sq is brazed on 9.0 mm sq metallization cuw is connected to v ee pin a1 index (0.50 mm full circle) 9.270 mm 9.085 mm 9.00 mm sq 7.20 mm sq 10.685 mm 2.50 mm 5.605 mm these lands are designed for discrete capacitor device 0603 size (1.6 x 0.8 mm) 2.50 mm 2.50 mm 2.50 mm marking area 2 marking area 1 4.335 mm 21.00 mm sq 7.20 mm sq 9.00 mm sq 2.50 mm 6.815 mm 9.270 mm 2.50 mm 10.685 mm 4.335 mm 2.50 mm 9.085 mm 2.50 mm cuw 7.2 mm sq is brazed on 9.0 mm sq metalization cuw is connected to v ee 5.605 mm capacitor discrete devices are 0603 size (1.6 x 0.8 mm) thickness 0.8 mm weight 3 - 4 mg each pin a1 index (0.50 mm full circle)
25 5404a?bdc?11/06 AT84AS008 5.1.3 cross section cbga 152 21x21 mm cross section 10 bits/2.2 gsps adc. external heatsink required low t? solder balls diam 0.76 mm on 1.27 mm grid combo lid soldered 9.27 mm sq 0.254 mm thick grounded al2o3 ceramic cuw heatspreader brazed on al2o3 at vee=-5 volt potential location for external heatsink 1.25 +/- 0.12 mm 0.65 mm 0.50 +/- 0.05 mm 1.27 mm 0.80 mm 0.25 0.15
26 5404a?bdc?11/06 AT84AS008 5.1.4 cbga 152 cavity, wirebonding and resistor pairs figure 5-6. cbga 152 cavity, wirebonding and resistor pairs 5.2 thermal and moisture characteristics 5.2.1 dissipation by conduction and convection the thermal resistance from junction to ambient rth ja is around 30 c/w. therefore, to lower rth ja it is mandatory to use an external heatsink to improve dissipation by convection and con- duction. the heatsink should be fixed in contact with the t op side of the package (cuw heatspreader over al2o3) which is at -5v. the heat sink needs to be electr ically isolated; using an adequate low rth electrical isolation. example : the thermal resistance fr om case to ambient rth ca is typically 4.0 c/w (0 m/s air flow or still air) with the heatsink depicted in figure 1, of dimensions 50mm 50mm 22mm (respectively l l h). global junction to ambient thermal resistance rth ja is: 4.35 c/w rth jc +2.0 c/w thermal grease resistance +4.0 c/w rth ca (case to ambient) + = 0.35 c/w total (rth ja ). 50 ? termination resistors soldered into the package cavity
27 5404a?bdc?11/06 AT84AS008 assuming: typical thermal resistance from junction to bottom of case rth jc is 4.35oc/watt (finite element method thermal simulation results).this value does not include thermal contact resistance between package and external heatsink (glue, paste, or thermal foil interface for example). as an example, use 2.0 c/w value for 50 m thickness of thermal grease. note: example of calculation of ambient temperature t a max to ensure t j max = 110 c: assuming rth ja = 10.35 c/w and power dissipation = 4.6w, t a max = t j - ( rth ja 4.6w) = 110 -(10.35 4.6) = 62.39 c t a max can be increased lowering rth ja with adequate air flow (2 m/s, for example). figure 5-7. black anodized aluminum heatsink glued on a copper base screwed on board (all dimensions in mm). cooling system efficiency can be monitored using the temperature sensing diodes, integrated in the device. 5.2.2 thermal dissipation by conduction only when external heatsink cannot be used the relevant thermal resistance is thermal resistance from junction to bottom of balls: rth j-bottom-of-balls . thermal path, in this case, is junction, then silicon, glue, cuw heatspreader, al2o3 of package, and balls (sn63pb37). finite element method (fem) with thermal simulator lead to rth j-bottom of balls = 12.3c/watt. this value assume pure conduction from junction to bot- tom of balls.(that is worst case, no radiati on and no convection applied). with such assumption the rth j- bottom-of-balls is user independent. to complete thermal analysis, user must add the thermal resistance from top of board (on which is soldered the device) to ambient, which value is user dependent (type of board, thermal via, area covered by copper in each layer of the board, thickness, airflow or cold plate are parameters to consider). 8.5 50 52 20 22 15 9 40 0.5 7.4 circular base (diam. 8.5 mm) cuw heat spreader tied to v ee = -5 v ai203 copper base with standoffs board holes for screw (diam. 2 mm) black anodized aluminium
28 5404a?bdc?11/06 AT84AS008 6. equivalent input/output schematics figure 6-1. equivalent analog input circuit and esd protection note: 100 ? termination mid point are located inside package cavity and dc coupled to ground. figure 6-2. equivalent analog clock input circuit and esd protection note: 100 ? termination mid point are on chip and ac coupled to ground through a 40 pf capacitor. 1 ma 1 ma vee = -5v die pads vin vinb termination resistors soldered into the package cavity 50 ? 2% gnd 50 ? 2% package pins esd 120 ff vee = -5v 1.5v vee = -5v esd 120 ff 50 ? controlled transmission line (bonding + package + ball) double pad 260 ff 50 ? controlled transmission line (bonding + package + ball) double pad 260 ff 50 ? 50 ? vee = -5v 150 ? 150 ? vee = -5v 40 pf 400 a 400 a vee = -5v double pad 260 ff esd 120 ff esd 215 ff esd 120 ff clk clkb double pad 260 ff double pad 260 ff mid vee = -5v
29 5404a?bdc?11/06 AT84AS008 figure 6-3. equivalent data output buff er circuit and esd protection figure 6-4. adc gain adjust equivalent input circuits and esd protection figure 6-5. b/gb and pgeb equivalent input schematics and esd protection 10.5 ma outb 50 ? 50 ? vplusd vplusd vplusd out pad 130 ff pad 130 ff esd 100 ff esd 100 ff esd 60 ff dvee = -5v esd 60 ff -+ vcc = 5v vee = -5v 1 k ? 20 ? ga vee = -5v pad 130 ff esd 75 ff esd 65 ff 0.9v gnd 0v 100 a 10 pf 100 a 5 k ? 1 k ? 2 k ? gnd gnd gnd b/gb vee = -5v vee = -5v esd 75 ff esd 65 ff pad 130 ff 250 a 250 ? -1.3v
30 5404a?bdc?11/06 AT84AS008 figure 6-6. drrb equivalent input schematic and esd protection figure 6-7. decb/diode equivalent input schematic and esd protection 200 ? 4.4 k ? gnd drrb gnd gnd vee = -5v vee = -5v -1.3v -2.6v 200 a 200 ? pad 130 ff esd 65 ff esd 75 ff 5 k ? 1 k ? 2 k ? gnd gnd gnd decb/diode vee = -5v vee = -5v esd + tsense 65 ff 130 ff 250 a 250 ? -1.3v
31 5404a?bdc?11/06 AT84AS008 7. definition of terms table 7-1. definition of terms term description fs max maximum sampling frequency sampling frequency for which enob < 6 bits fs min minimum sampling frequency sampling frequency for which the adc gain has fallen by 0.5db with respect to the gain reference value. performances are not guaranteed below this frequency ber bit error rate probability to exceed a specified error threshold for a sample at maximum specified sampling rate. an error code is a code that differs by more than 4 lsb from the correct code fpbw full power input bandwidth analog input frequency at which the fundamental component in the digitally reconstructed output waveform has fallen by 3 db with respect to its low frequency value (determined by fft analysis) for input at full-scale -1 db (-1 dbf s ) ssbw small signal input bandwidth analog input frequency at which the fundamental component in the digitally reconstructed output waveform has fallen by 3 db with respect to its low frequency value (determined by fft analysis) for input at full-scale -10 db (- 10 dbf s ) sinad signal-to-noise and distortion ratio ratio expressed in db of the rms signal amplitude, set to 1db below full- scale (-1 dbf s ), to the rms sum of all other spectral components, including the harmonics except dc snr signal-to-noise ratio ratio expressed in db of the rms signal amplitude, set to 1db below full- scale, to the rms sum of all other sp ectral components excluding the twenty five first harmonics thd total harmonic distortion ratio expressed in db of the rms sum of the first twenty five harmonic components, to the rms input signal amplitude, set at 1 db below full-scale. it may be reported in db (i.e, related to converter -1 db full-scale), or in dbc (i.e, related to input signal level sfdr spurious free dynamic range ratio expressed in db of the rms signal amplitude, set at 1db below full- scale, to the rms value of the highest spectral component (peak spurious spectral component). the peak spurious component may or may not be a harmonic. it may be reported in db (i.e., related to converter -1 db full-scale), or in dbc (i.e, related to input signal level) enob effective number of bits where a is the actual input amplitude and f s is the full-scale range of the adc under test dnl differential non-linearity the differential non-linearity for an output code i is the difference between the measured step size of code i and the ideal lsb step size. dnl (i) is expressed in lsbs. dnl is the maximum value of all dnl (i). dnl error specification of less than 1 lsb guaran tees that there are no missing output codes and that the transfer function is monotonic inl integral non-linearity the integral non-linearity for an output code i is the difference between the measured input voltage at which the tr ansition occurs and the ideal value of this transition. inl (i) is expressed in lsbs, and is the maximum value of all inl (i) ta aperture delay delay between the rising edge of the differential clock inputs (clk,clkb) (zero crossing point), and the time at which (vin,vinb) is sampled enob sinad 176 ? ? 20 a fs 2 ? ------------- log + 602 ? -------------------------------------------------------------------------- =
32 5404a?bdc?11/06 AT84AS008 jitter aperture uncertainty sample to sample variation in aperture delay. the voltage error due to jitter depends on the slew rate of the signal at the sampling point ts settling time time delay to achieve 0.2% accuracy at the converter output when a 80% full-scale step function is applied to the differential analog input ort overvoltage recovery time time to recover 0.2% accuracy at t he output, after a 150% full-scale step applied on the input is reduced to midscale tod digital data output delay delay from the rising edge of the differential clock inputs (clk,clkb) (zero crossing point) to the next point of cha nge in the differential output data (zero crossing) with specified load tdr data ready output delay delay from the falling edge of the differential clock inputs (clk,clkb) (zero crossing point) to the next point of ch ange in the differential data ready output (zero crossing) with specified load td1 time delay from data transition to data ready general expression is td1 = tc1 + tdr - tod with tc = tc1 + tc2 = 1 encoding clock period td2 time delay from data ready to data general expression is td2 = tc2 + tdr - tod with tc = tc1 + tc2 = 1 encoding clock period tc encoding clock period tc1 = minimum clock pulse width (high) tc = tc1 + tc2tc2 = minimum clock pulse width (low) tpd pipeline delay number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the tod) trdr data ready reset delay delay between the falling edge of the data ready output asynchronous reset signal (ddrb) and the reset to digital zero transition of the data ready output signal (dr) tr rise time time delay for the output data signals to rise from 20% to 80% of delta between low level and high level tf fall time time delay for the output data signals to fall from 20% to 80% of delta between low level and high level psrr power supply rejection ratio ratio of input offset variation to a change in power supply voltage nrz non return to zero when the input signal is larger than the upper bound of the adc input range, the output code is identical to the ma ximum code and the out of range bit is set to logic one. when the input signal is smaller than the lower bound of the adc input range, the output code is identical to the minimum code, and the out of range bit is set to logic one. (it is assumed that the input signal amplitude remains within the absolute maximum ratings) imd inter-modulation distortion the two tones inter-modulation distortion (imd) rejection is the ratio of either input tone to the worst third order inter-modulation products npr noise power ratio the npr is measured to characterize the adc performance in response to broad bandwidth signals. when applying a notch-filtered broadband white- noise signal as the input to the adc under test, the noise power ratio is defined as the ratio of the average out-of-notch to the average in-notch power spectral density magnitudes for the fft spectrum of the adc output sample test vswr voltage standing wave ratio the vswr corresponds to the adc input insertion loss due to input power reflection. for example a vswr of 1.2 corresponds to a 20 db return loss (i.e. 99% power transmitted and 1% reflected) table 7-1. definition of terms (continued) term description
33 5404a?bdc?11/06 AT84AS008 8. AT84AS008 application information 8.1 timing information 8.1.1 timing value for AT84AS008 timing values are defined in section 3.3 . timing values are given at package inputs/outputs, taking into account package transmission line, bond wire, pad and esd protections capacitance, and specified termination loads. evaluation board propagation delays in 50 ? controlled impedance traces are not taken into account. apply proper derating values corresponding to termination topology. 8.1.2 propagation time considerations tod and tdr timing values are given from packag e pin to pin and do not include the additional propagation times between device pins and input/ output termination loads. for the evaluation board, the propagation time delay is 6.1 ps/mm (155 ps/inch) corresponding to 3.4 dielectric constant (at 10ghz) of the ro4003 used for the board. if a different dielectric layer is used (for instance teflon), please use appropriate propagation time values. td1 and td2 do not depend on pr opagation times because they are differential data ( see ?definition of terms? on page 31. ). td1 and td2 are also the most straightforward data to measure, because it is differential: td can be measured directly onto termination lo ads, with matched oscilloscope probes. 8.1.3 tod-tdr variation over temperature values for tod and tdr track each other over temperature (1 percent variation for tod - tdr per 100 degrees celsius temperature variation). therefore tod - tdr variation over tempera- ture is negligible. moreover, the internal (on chip) skews between each data tods and tdr effect can be considered as negligible. consequently, minimum values for tod and tdr are never more than 100 ps apart. the same is true for the tod and tdr maximum values. however, external tod - tdr values may be dict ated by total digital data skews between every tods (each digital data) and tdr: mcm board, bonding wires and output line length differ- ences, and output termination impedance mismatches. the external (on board) skew effect has not been taken into account for the specification of the minimum and maximum values for tod - tdr. 8.1.4 principle of operation the analog input is sampled on the rising edge of external clock input (clk,clkb) after ta (aperture delay). the digitized data is availabl e after 4 clock periods latency (pipeline delay (tpd)), on clock rising edge, after typical propagation delay tod. the data ready differential output signal frequency (dr, drb) is half the exter nal clock frequency, it switches at the same rate as the digital outputs. the data ready output signal (dr, drb) switches on external clock falling edge after a propagation delay tdr. if tod = tdr, the rising edge (true-false) of th e differential data ready signal is placed in the middle of the output data valid window. this gives maximum setup and hold times for external data acquisition. a master asynchronous reset in put command drrb (ecl compatib le single-ended input) is available for initializing the differential data re ady output signal (dr,drb). this feature is man-
34 5404a?bdc?11/06 AT84AS008 datory in certain applications using interleaved adcs or using a single adc with demultiplexed outputs. without data ready signal initialization, it is impossible to store the output digital data in a defined order. when used with at84cs001 1:2/1:4 10 bit dmux, it is not required to initialize the data ready, as this device can start on either clock edge. 8.2 principle of data ready sign al control by drrb input command 8.2.1 data ready output signal reset the data ready signal is reset on falling edge of drrb input command, on ecl logical low level (-1.8v). drrb may also be tied to v ee = -5v for data ready output signal master reset. so long drrb remains at logica l low level, (or tied to v ee = -5v), the data ready output remains at logical zero and is independent on the external free running encoding clock. the data ready output signal (dr,drb) is reset to logical zero after trdr. trdr is measured between the -1.3v point of the falling edge of drrb input command and the zero crossing point of the differential data ready output signal (dr,drb).the data ready reset command may be a pulse of 1 ns minimum time width. 8.2.2 data ready output signal restart the data ready output signal restarts on drrb command rising edge, ecl logical high levels (-0.8v). drrb may also be grounded, or is allowed to float, for normal free running of the data ready output signal. the data ready signal restart sequence depends on the logical level of the exter- nal encoding clock, at drrb rising edge instant: 1. the drrb rising edge occurs when the external encoding clock input (clk,clkb) is low: the data ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay time tdr = 360 ps already de fined here above. 2. the drrb rising edge occurs when the external encoding clock input (clk,clkb) is high: the data ready output first rising edge occurs after one clock period on the clock falling edge, and a delay tdr = 360 ps. consequently, as the analog input is sampled on th e clock rising edge, the first digitized data corresponding to the first acquisi tion (n) after data ready signal restart (rising edge) is always strobed by the third rising edge of the data ready signal. the time delay (td1) is specified between the last point of a change in the differential output data (zero crossing point) to the rising or falling edge of the differential data ready signal (dr,drb) (zero crossing point). note: for normal initialization of data ready output signal, the external encoding clock signal frequency and level must be controlled. it is reminded that the minimum encoding clock sampling rate for the adc is 150 msps, due to internal t/h droop rate. consequently the clock cannot be stopped without corrupting the current held data.
35 5404a?bdc?11/06 AT84AS008 8.2.3 timing diagram with data ready reset figure 8-1. AT84AS008 timing diagram (2 gsps clock rate) ? data ready reset, clock held at low level figure 8-2. AT84AS008 timing diagram (2 gsps clock rate) - data ready reset, clock held at high level 8.3 analog inputs (vin/vinb) 8.3.1 static issues: differential versus single-ended (full-scale inputs) the adc front-end track and hold differential preamplifier has been designed in order to be entered either in differential mode or single-ended mode, up to maximum operating speed (2.2 gsps), without affecting dynamic performances (does not request a single to differential balun). in single-ended input configuration, the in-phase full-scale input amplitude is 0.5v peak-to-peak, centered on 0v. (or -2 dbm into 50 ? ). n - 4 n - 3 n - 2 n - 1 n n + 1 v in /v inb clk/clkb digital outputs data ready dr/drb data ready reset ta = 160 ps n n + 1 n + 2 n + 3 n - 5 tod = 360 ps tdr = 360 ps trdr = 300 ps 1 ns tc = 500 ps tc1 tc2 tpd = 4.0 clock period tod = 360 ps 500 ps tdr = 360 ps td1 = tc1 + tdr - tod = tc1 = 250 ps td2 = tc2 + tod - tdr = tc2 = 250 ps n - 4 n - 3 n - 2 n - 1 n n + 1 n - 5 500 ps td2 = tc2 + tod - tdr = tc2 = 250 ps td1 = tc1 + tdr - tod = tc1 = 250 ps tdr = 360 ps tpd = 4.0 clock periods tod = 360 ps trdr = 300 ps 1 ns tdr = 360 ps tod = 360 ps ta = 160 ps n n + 1 n + 2 n + 3 tc = 500 ps tc1 tc2 v in /v inb clk/clkb digital outputs data ready dr/drb data ready reset
36 5404a?bdc?11/06 AT84AS008 figure 8-3. typical single-ended analog input configuration (full-scale) the analog input full-scale range is 0.5v peak to peak (vpp), or -2 dbm into the 50 ? (100 ? dif- ferential) termination resistor. in differential mode input configuration, that means 0.25v on each input, or 125 mv around zero volt. the input common mode is ground. figure 8-4. differential inputs volt age span (full-scale) 8.3.2 dynamic issues: input impedance and vswr the AT84AS008 analog input features a 100 ? (2%) differential input impedance (2 50 ? // 0.3 pf): each analog input (vin,vinb) is terminated by 50 ? single-ended (100 ? differential) resistors (2% matching) soldered into t he package cavity. the ad c package analog inputs transmission lines feature a 50 ? controlled impedance. each single-ended die input pad capac- itance (taking into account esd protection) is 0.3 pf. this leads to a global input vswr (including ball, package and bounding) of less than 1.2 from dc up to 2.5 ghz. 8.4 clock inputs (clk/clkb) the AT84AS008 clock inputs are designed for eith er single-ended or differential operation. the AT84AS008 clock inputs are on- chip 100 ? (2 50 ? ) differentially termin ated. termination mid point is ac coupled to ground through 40 pf on chip capacitor. therefore either ground or differ- ent common modes could be used (ecl, lvds). however logic ecl or lvds square wave cl ock generators are not recommended because of poor jitter performances. 500 mv full-scale analog input +250 mv -250 +250 mv vin vinb = 0v t mv +125 -125 500 mv full-scale analog input t vin vinb +250 mv -250 mv 0v
37 5404a?bdc?11/06 AT84AS008 furthermore, the propagation times of the biasing tees used to offset the common mode voltage to ecl or lvds levels may not match. a very low phase noise (low jitter) sinewave input signal should be used for enhanced snr performance, when digitizing high fr equency analog inputs. typically, using a sinewave oscillato r featuring -135 dbc/hz phase no ise, at 20 khz from carrier, a global jitter value (including adc + generator) of less than 200 fs rms has been measured. if clock signal frequency is at fixed rates, it is recommended to narrow band filter the signal to improve jitter performance. note : the clock input buffer 100 ? termination load is on chip, mid point ac coupled (40pf) to chip ground plane, whereas the analog input buffer 100 ? termination is soldered inside package cavity, mid point dc coupled to package ground plane. therefore, driving the analog input in single ended does not perturb the chip ground plane, (since termination mid point is con- nected to package ground plane). but driving the clock input in single ended will pe rturb the chip ground plan e, (since termination mid point is ac coupled to chip ground plane). ther efore, it is required to drive the clock input in differential, for minimum chip ground plane per turbation (4 dbm max operating recommended). typical clock input power is 0 dbm. the minimu m operating clock input power is -4 dbm (equiv- alent to 250 mv minimum swing amplitude), to avoid snr performances degradations linked to clock signal slew rate. a single to differential balun with sqrt (2) ratio may be used (featuring 50 ? input impedance with 100 ? differential termination). for instance: 4 dbm is equivalent to 1 vpp into 50 ? and 1.4 vpp into 100 ? termination (secondary) 0 dbm is equivalent to 0.632 vpp into 50 ? and 0.632 sqrt (2) = 0.894 vpp into 100 ? termination (secondary), 0.226v each clock input recommended clock inputs common mode is ground. 8.4.1 differential clock inputs voltage levels (0 dbm typical) figure 8-5. differential clock inputs (ground common mode): recommended v +0.23 -0.23 clk clkb 0v t
38 5404a?bdc?11/06 AT84AS008 8.4.2 equivalent single-ended clock i nputs voltage levels (0 dbm typical) figure 8-6. single-ended clock input (ground common mode) 8.5 noise immunity information circuit noise immunity performance begins at design level. efforts have been made on the design in order to make the device as insensitive as possible to chip environment perturbations resulting from the circuit itself or induced by external circuitry (cascode stages isolation, internal damping resistors, clamps, internal on chip decoupling capacitors.) furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced noise immunity by common mode noise rejection. common mode noise voltage induced on the differenti al analog and clock inputs will be ca ncelled out by these balanced differ- ential amplifiers. moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs: the anal og inputs and clock inputs of the ts83102g0b device have been surrounded by ground pins, which must be directly connected to the external ground plane. 8.6 digital outputs: terminat ion and logic compatibility each single-ended output of the AT84AS008 differential output buffers are internally 50 ? termi- nated, and feature a 100 ? differential output impedance. the 50 ? resistors are connected to the v plusd digital power supply. the AT84AS008 output buffers are designed to drive 50 ? con- trolled impedance lines properly terminated by a 50 ? resistor. a 10.5 ma bias current flowing alternately into one of the 50 ? resistors when switching ensures a 0.25v single-ended voltage drop across the resistor (0.5v differential) each single-ended output transmission line lengt h must be kept identical (keep < 3 mm). mis- matches in the differential line lengths may c ause output differential common mode variation. it is recommended to bypass the midpoint of the differential 100 ? termination with a 47 pf capacitor to avoid common mode perturbation in case of slight mismatch in the differential out- put line lengths. see recommended-termination scenarios here below. v +0.32 -0.32 clk clkb 0v t
39 5404a?bdc?11/06 AT84AS008 note: since output buffers feature 100 ? differential output impedance, it is possible to drive directly high input impedance storing registers, without terminating the 50 ? transmission lines. in time domain, th is means that th e incident wave will reflect at the 50 ? transmission line output and travel back to the 50 ? data output buffer. since the buffer output impedance is 50 ? , no back reflection will occur and output swing will be doubled. v plusd digital power supply settings: for differential ecl digital output levels: v plusd should supplied with -0 .8v (or connect it to ground via a 5 ? resistor to ensure the -0.8v voltage drop). for lvds digital output logic compatibility, v plusd should be tied to 1.45v (75mv). 8.6.1 ecl differential output termination configurations figure 8-7. 50 ? terminated dif ferential outputs (recommended) figure 8-8. unterminated dif ferential outp uts (optional) 10.5 ma zc = 50 ? out vplusd = - 0.8v zc = 50 ? 50 ? 50 ? outb 50 ? 50 ? vol typ = -1.17v voh typ = -0.94v differential output swing: 0.23v = 0.46 vpp common mode level = -1.05v 47 pf 10.5 ma zc = 50 ? out vplusd = -0.8v zc = 50 ? outb 50 ? ? vol typ = -1.4v voh typ = -0.94v differential output swing: 0.46v = 0.92 vpp common mode level = -1.17v
40 5404a?bdc?11/06 AT84AS008 8.6.2 lvds differential output loading configurations figure 8-9. 50 ? terminated diffe rential outputs figure 8-10. unterminated dif ferential outp uts (optional) 8.6.3 lvds logic compatibility lvds format (cf ieee std 1596.3- 1994): 1125mv< common mode <1275mv and 250mv< output swing< 400mv. 10.5 ma zc = 50 ? out vplusd = 1.45v zc = 50 ? 50 ? 50 ? outb 50 ? 50 ? vol typ = 1.09v voh typ = 1.31v differential output swing: 0.23 vp = 0.46 vpp common mode level = 1.20v 47 pf 10.5 ma zc=50 ? out vplusd = 1.45v zc=50 ? outb 50 ? ? vol typ = 0.85v voh typ = 1.31v differential output swing: 0.46v = 0.92 vpp common mode level = -1.08v common mode (each single-ended output swing max voh max = 1.575v swing min voh min = 1.575v vol max = 1.075v vol min = 0.825v cm max = 1275 mv cm min = 1125 mv output swing max = 300 mvp output swing min = 200 mvp 0v true-false output false-true output swing max
41 5404a?bdc?11/06 AT84AS008 8.7 adc main functions 8.7.1 out of range bit (or/orb) it goes to logical high state when the input exceeds the positive full-scale or falls below the neg- ative full-scale. when the analog input exceeds the positive full-scale, the digital outputs remain at high logical state, with (or,orb) at logical one. when the analog input falls below the nega- tive full-scale, the digital outputs remain at logical low state, with (or,orb) at logical one again. 8.7.2 bit error rate (ber) the AT84AS008 internal regeneration latches indecisi on (for inputs very close to latches thresh- old) may produce errors in the logic encoding circuitry and leading to large amplitude output errors. this is due to the fact that the latches are r egenerating the internal analog residues into logical states with a finite voltage gain value (av) within a given positive amount of time d(t): av = exp(d(t)/ ), with the positive feedback regeneration time constant. the AT84AS008 has been designed for reducing the probability of oc currence of such errors to 10 -12 . a standard technique for reducing the amplitude of such errors down to 1 lsb consists in setting the digital output data in gray code format. though the AT84AS008 has been designed for featuring a bit error rate of 10 -12 with a binary output format. 8.7.3 gray or binary output data format select it is possible for the user to choose between the binary or gray output data format, in order to reduce the amplitude of such errors when occurring, by storing gray output codes. digital data format selection: binary output format if b/gb is floating or gnd. gray output format if b/gb is connected to v ee . 8.7.4 pattern generator function the pattern generator function (enabled by connecting pin a9 pgeb to ecl low or to v ee = -5v) allows to check rapidly the adc operation thanks to a checker board pattern delivered internally to the adc. each output bit of the adc should toggle from 0 to 1 successively, giving sequences such as 0101010101 (strobed by falling edge of dr) a nd 1010101010 (s trobed by rising edge of dr) every 2 clock cycles. 8.7.5 decb/diode: junction temperature monitoring and output decimation enable the decb/diode pin is provided for both decima tion function enable and die junction tempera- ture monitoring. when set to ecl low or v ee = -5v, the adc runs in decimation by 32 mode (1 data out of 32 is output from the adc, thus reducing the data rate by 32). when the decb/diode pin is left floating or ecl high, then the adc is said to be in normal mode of operation (output data are not decimated) and can be used for die junction temperature monitoring only. if the user does not intend to use the die junction temperature monitoring function, the decb/diode pin (a10) has to be left either floating or connected to ground.
42 5404a?bdc?11/06 AT84AS008 the decimation function can be used for debug of the adc at initial stages. this function indeed allows to reduce the adc output rate by 32, thus allowing for a quick debug phase of the adc at max speed rate and is compatible with industrial testing environment. when active, this function makes the adc output only 1 out of 32 data, thus resulting in a data rate which is 32 times slower than the clock rate. note: the adc decimation test mode is different fr om the pattern generator function, which can be used to check the adc outputs. 8.7.6 external configurations description because of the use of 1 internal diode-mounted transistor (used for j unction temperature moni- toring), the user has to implement external he ad-to-tail protection diodes to avoid potential reverse currents flows which may damage the internal diode component. two external configurations are possible: configuration 1: allowing both junction temperature monitoring and output data decimation. configuration 2: allowing junction temperature monitoring only. configuration 1: allowing both junction temperature monitoring and output data decimation. this external configuration a llows to apply the requested levels to activate output data decima- tion (ecl low or v ee = -5v) and at the same time monitor the junction temperature diode (this explains why seven protection diodes are needed in the other direction, as described in the fol- lowing figure). figure 8-11. recommended diode pin implementation allowing for both die junction tempera- ture monitoring function and decimation mode. figure 8-12. diode pin implementation for decimation activation configuration 2: junction temperature moni toring only (in this mode adc decimation can- not be activated). note: in preliminary specification e2v recommended t he use of 2 3 head-to-tail protection diodes. final updated configuration is described in figure 19 here below. adc pin a10 gnd vee = -5 v
43 5404a?bdc?11/06 AT84AS008 figure 8-13. diode pin implementation of die juncti on temperature monitoring function only figure 8-14. junction temperature diode transfer function the forward voltage drop, (vdiode) across diode component, versus junction temperature, (including chip parasitic resistance), is given below (idiode = 1 ma): note: the operating die junction temperature must be kept below 125 c, to ensure long term device reliability. adc pin 1ma a10 gnd vgnd v vdiode idiode ignd 740 750 760 770 780 790 800 810 820 830 840 850 860 870 880 890 900 910 920 930 940 950 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 jonction temperature (?c) diode voltage (mv) tamb avec radiateur
44 5404a?bdc?11/06 AT84AS008 8.7.7 adc gain control the adc gain is adjustable by the means of the pin r9 of cbga package. the gain adjust transfer function is given below: 8.7.8 sampling delay adjust sampling delay adjust (sda pin) allows to fi ne tune the sampling adc aperture delay tad around its nominal value (160 ps). this functionality is enabled thanks to the sdaen signal, which is active when tied to v ee and inactive when tied to gnd. this feature is particularly interesting for interleaving adcs to increase sampling rate. the variation of the delay around its nominal valu e as a function of the sda voltage is shown in the following graph (simulation result): figure 8-15. typical tuning range is 120 ps for applied contro l voltage varying between -0 .5v to 0.5v on sda pin note: the variation of the delay in function of the temperature is negligible. 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 v ga gain adjust voltage (v) adc gain min typical 400 p 300 p 200 p 100 p -500 m -400 m -300 m -200 m -100 m 0.00 100 m 200 m 300 m 400 m 500 m delay in the variable delay cell at 60 c delay(s)
45 5404a?bdc?11/06 AT84AS008 9. ordering information 10. appendix 10.1 life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be ex pected to result in personal injury. e2v cus- tomers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify e2v for any damages resulting from improper use or sale. part number package temperature range screening level comments AT84AS008cgl cbga152 commercial c grade 0 c < tc, tj < 90 c standard AT84AS008vgl cbga152 industrial v grade -20 c < tc, tj < 110 c standard AT84AS008gl-eb cbga 152 ambient prototype evaluation board (delivered with a heat sink) datasheet status status validity objective specification this datasheet contains target an d goal specifications for discussion with the client and application validation before design phase target specification this datasheet contains target an d goal specifications for product development valid during the design phase preliminary specification alpha-site this datasheet contains preliminar y data. additional data may be published an a later date and could include simulation results valid before the characterization phase preliminary specification beta-site this datasheet also contains characterization results valid before the industrialization phase product specification this datasheet c ontains final product specifications valid for production purposes limiting values limiting values given are in accordance with the absolute maxi mum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sect ions of the specification is not implied. exposure to limiti ng values for extended periods may affect device reliability application information where application information is given, it is advis ory and does not form part of the specification
46 5404a?bdc?11/06 AT84AS008
i 5404a?bdc?11/06 AT84AS008 1 description ............ .............. .............. .............. .............. .............. ............. 2 2 functional description ............ ................ ................. ................ ............... 2 3 specifications ........... ................ ................ ................. ................ ............... 3 3.1absolute maximum ratings .......................................................................................3 3.2recommended conditions of use .............................................................................4 3.3electrical characteristics ...........................................................................................5 3.4explanation of test levels ........................................................................................9 3.5functions description ..............................................................................................10 3.6timing diagram .......................................................................................................11 3.7coding ..................................................................................................................... 11 4 characterization results .... .............. .............. .............. .............. ........... 12 4.1nominal conditions .................................................................................................12 4.2full power input bandwidth .....................................................................................12 4.3vswr versus input frequency ...............................................................................12 4.4step response ........................................................................................................13 4.5dynamic performance versus sampling frequency ...............................................13 4.6dynamic performance versus input frequency ......................................................14 4.7signal spectrum ......................................................................................................15 4.8dynamic performance sensitivity versus temperature and power supply ............16 4.9sfdr performance with and without added dither ................................................17 4.10dual tone performance ........................................................................................17 4.11npr performance ..................................................................................................19 5 pin description ......... ................ ................ ................. ................ ............. 20 5.1package description ................................................................................................22 5.2thermal and moisture characteristics .....................................................................26 6 equivalent input/output schem atics ............ .............. .............. ........... 28 7 definition of terms ........... ................ .............. .............. .............. ........... 31 8 AT84AS008 application information ...... ................. ................ ............. 33 8.1timing information ...................................................................................................33 8.2principle of data ready signal control by drrb input command .........................34 8.3analog inputs (vin/vinb) ........................................................................................35 8.4clock inputs (clk/clkb) ........................................................................................36 8.5noise immunity information .....................................................................................38 8.6digital outputs: termination and logic compatibility ..............................................38
ii 5404a?bdc?11/06 AT84AS008 8.7adc main functions ................................................................................................41 9 ordering information .......... .............. .............. .............. .............. ........... 45 10 appendix ................ .............. .............. .............. .............. .............. ........... 45 10.1life support applications .......................................................................................45
5404a?bdc?11/06 whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the conse- quences of any use thereof and also reserves the right to c hange the specification of goods wit hout notice. e2v technologies ac cepts no liability beyond that set out in its standard conditions of sale in respec t of infringement of third party patents arising from the use o f tubes or other devices in accordance with information contained herein.

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